Since Intel bought Altera for a tremendous amount of money a couple of years ago,
(19459003) ed: $ 16.7B The FPGA portfolio that came out was largely a product of -Intel days. Today, however, this is changing as Intel announces its first fully-designed Intel FPGA built on its own internal 10nm process with the Agilex brand. This new product line will be released later this year for sampling and will offer a mix of analogue, digital, custom IO and eASIC variants on a single platform.
For users familiar with the Intel FPGA family, Agilex's new portfolio is an upgrade of the generation over the current Stratix 1
The Agilex FPGA is based on similar design principles with Stratix – a centralized FPGA block with gate features and external links to several different customer-based technologies. For these external connections, Intel uses Embedded Multi-Die Interconnect Bridge (EMIB) technology, which can be extended to other chiplets in the examples. Some of Intel's offerings include high-speed memory (HBM), next-generation 112G, PCIe Gen 5.0 root complexes, Compute eXpress Link interfaces (via PCIe 5.0), additional CPU cache and other chiplets / IP connections. by the customer. To add all this, Agilex will also support Intel's Optane DC permanent memory.
One of the major updates to the FPGA family is due to the acquisition of eASIC by Intel. Intel actually worked with eASIC for several years, but in 2018 it bought the company to provide additional synergies in its software portfolio. With Agilex, the first stage of this vision is ready to be delivered – customers who want fast IP deployment can choose to work with Intel's eASIC for chipset or fusion merger into FPGAs faster than the customer can Do Itself, and Utilizing Intel's Own Product Design Chain
Using PCIe Gen 5.0 is also a great element of Agilex as it allows customers to connect directly to future PCIe 5.0 host devices but also allows the new Compute Intel's eXpress Link. technology based on PCIe 5.0 physical standards. The CXL is Intel's own cache device that works together (or competes with whomever you ask) with GenZ and CCIX. Given Intel's comments on CXL, it is clear that when PCIe 5.0 is ubiquitous, it intends to import its portfolio of additional cards into CXL, PCIe 5.0, or both. And one of Intel's great themes recently is its movement in discrete graphics that can benefit from it. It seems, however, that Agilex may be the first to take advantage of the new Intel standard when it is ready – Intel has so far stated that Agilex will support UPI as the basic cache connectivity option.
As always with the FPGA market, Intel is targeting the usual suspects that could use them: networks, cloud, embedded, and enterprise. The latest FPGAs in this area are related to end-user deployment as well as a network, so we can expect to see Intel's research into new hardware in these areas. AI is also important as Intel wants to announce that Agilex's portfolio will have enhanced support for bfloat16 and other low-precision formats, even INT2. They will be managed through Intel's OneAPI strategy and the company claims that although the FPGA can be used for AI, it will work with Nirvana and Movidius instead of competing.
One element that was interesting during our discussions with Intel for Agilex is that the company mentions 3D stacking and integration. I was wondering if this is just a mention of HBM, or something more detailed, like Foveros technology, which the company demonstrated at the end of 2018. Intel said 3D integration would be an expected development of the product line and the future with its second-generation Agilex . Perhaps it is not expected to be a date when this will happen, but it is still interesting.
Agilex will be available in three versions: F, I and M, with the exact support listed below. The Intel Quartus Prime software will support these variants from April 2019, and the first F-series will be available from Q3 2019.